Data Types in SystemVerilog

Introduction of Data Types:

SystemVerilog introduces new data types that are synthesizable and should make RTL descriptions easier to write and understand. Many of these will be familiar to C programmers. The idea is that algorithms modeled in C can more easily be converted to SystemVerilog if the two languages have the same data types.

Enumeration

• Enumeration, commonly called Enum, is a special data type introduced in SystemVerilog. This data type is a user-defined data type which means that a new data type can be created using Enum. Let’s talk about Enum and what kind of benefits it holds in writing complex code.
• Enumeration/Enum is a data type that assigns names to the integer constants. These are used to simplify the code and make it easier to read and manage. Also, ENum is synthesizable in SystemVerilog and thus can be used for design as well as test bench code.
• enum <data-type>{<elements>}<name>;
• enum {IDLE, SETUP, ACCESS}state; // example
• SystemVerilog has a rarely used feature that can totally do this. Example: enum { REG[0:3]}regname_e;
• If the value for an element is not mentioned explicitly it will automatically take the incremented value of the previous element for which the value is mentioned.
• In test benches, Enums can be used to create knobs for configuring the test bench. The use of enums in test benches will be discussed in later parts where we will discuss test benches.
• Enumeration In_built functions:
  • first() – return the value of the first element of the Enum.
  • last() – returns the value of the last element of the Enum.
  • prev(int N) – returns the value of the Nth element before the current element of Enum.
  • next(int N) – returns the value of the Nth element after the current element of Enum.
  • num() – returns the number of the element in the Enum.
  • name() – returns the name of the element.

Arrays

An array is a group of variables having the same data type. It can be accessed using an index value. An index is a memory address and the array value is stored at that address. In SystemVerilog, we can write arrays, which have either a fixed number of elements or a variable number of elements.

Types of an array:

• Fixed-size array – A fixed array is an array for which the size or length is determined when the array is created and/or allocated. A dynamic array is a random access, variable-size list data structure that allows elements to be added or removed. (Ex. int Array[8][32]: is the same as int Array[0:7][0:31];)
• Single Dimensional Array – Ex. int arr[3]; and int arr[2:0];
• Multidimensional Array – In a list of multi-dimensions, the rightmost one varies more rapidly than the leftmost one. The packed dimension varies more rapidly than the leftmost one. A packed dimension varies more rapidly than an unpacked.
  • Ex. bit[3:0]array_1[2:0][4:0]; // declaration
  • array_1[0][0] = 'b3;
  • array_1[0][1] = 'b7;
• Packed Array – Packed arrays in SystemVerilog are designed for storing and manipulating bit-level data efficiently. They provide a compact representation of data and allow designers to perform bitwise operations easily. Packed arrays (which are basically vectors) are typically synthesizable. Packed arrays use contiguous memory, where each element occupies the minimum number of bits required by the data type. This makes them ideal for applications involving bit-level manipulations, such as digital signal processing, image processing, and protocol implementations.
  • Example: reg [5:0] array; //is packed dimension
  • bit [2:0][3:0] array;
• Unpacked Array – An unpacked array refers to the dimension mentioned after the variable pr object name. Unpacked arrays use separate memory locations for each element. This allows them to handle complex data structures, such as arrays of structures or arrays of user-defined types, enabling efficient storage and access to non-bit data. arrays provide designers with powerful tools to organize and manipulate data in hardware designs. When working with arrays, one crucial decision to make is whether to use packed arrays or unpacked arrays. Each type has its own advantages and use cases, and understanding the differences between them is essential for making informed design decisions. Let us explore the characteristics of packed and unpacked arrays in SystemVerilog, discuss their respective strengths, and provide guidelines to help designers choose the most suitable array type for their specific design requirements.
  • Example: reg arr [3:0]; //unpacked dimension
  • int arr [2:0][3:0];
• Dynamic Arrays – A dynamic array is a random access, variable-size list data structure that allows elements to be added or removed. It is supplied with standard libraries in many modern programming languages. Dynamic arrays overcome a limit of static arrays, which have a fixed capacity that needs to be specified at allocation.
  • Example: <datatype><array_name>[] = {<elements of array>}
  • bit [0:3] arr [];
  • arr = new[size of array];
• Associative Arrays – Associative arrays are an extension of dynamic arrays which provide more flexibility in the way in which data can be stored. In associative arrays, the index can be of any data type including strings which makes it very beneficial for certain scenarios. Associative arrays give you another way to store information. When the size of the collection is unknown or the data space is sparse, an associative array is a better option. Index Can Be of Any Packed Type, String, or Class. Associative elements are stored in an order that ensures the fastest access.
  • Example: data_type array_1 [ key_type];
  • Associate Arrays Methods: num(), delete(), exist(), first(), last(), Next(), prev()
• Array Manipulation Methods – SystemVerilog provides built-in methods for array reduction, ordering, locator, and iterator index querying. In array manipulation methods, it iterates over array elements and evaluates the expression using the ‘with’ clause.
  • Example: array.find(y) with (y.color == BLUE);//with local variable
    • array.find with (item.color == BLUE);//without local variable
  • Array locator methods operate on queues and unpacked arrays, but their return type is a queue.
    • Search an index or elements of the array.
    • Array traversal in an unspecified order.
  • If no elements satisfy the given expression or the array is empty (in the case of a queue or dynamic array), then an empty queue is returned.
• Queues – A SystemVerilog is a First In First Out Scheme that can have a variable size to store elements of the same data type. A queue is a variable size and ordered collection of elements (homogenous element). It is considered the same as a single-dimensional unpacked array that grows and reduces automatically if it is a bounded queue. Queue is an analog to a one-dimensional array that grows and shrinks automatically.
  • Example: <data_type><q_name> [$];
    • <data_type><q_name>[$:<size>];

Structures – The SystemVerilog struct groups the data types of multiple types. A structure is a container data type which is a collection of variables of different data types. The entire group can be referenced as a whole, or the individual data type can be referenced by name. An array contains elements of the same data type. This makes structures different from an array.

• Example:
  • struct {
    • <Data type> <member 1>;
    • <Data type> <member 2>;
    • ...;
  • }<struct_name>;
  • The type def keyword allows the creation of multiple sets of information with different reference handles.
    • Example: typedef struct {bit[3:0];
      • byte addr;
      • int data;} instruction
    • SystemVerilog provides two types of structures:
      • Packed Structure – Similar to a packed array, if memory allocated for variables in a structure is contiguous, then it is called a packed structure. Only packed data types are allowed in packed structures. A string is not a packed data type, so code will not compile. To use string as a data type in structure, unpack structures can be used. The “packed” keyword is used to declare a packed structure.
        • Example: {bit[0:3] c; byte b; int a;} my_struct
      • Unpacked Structure – An unpacked structure is not as memory efficient as packed data structures. By default, a structure is unpacked in nature.
        • Example: struct_example
          • typedef struct {
          • string name;
          • bit[31:0] salary;
          • integer id;
        • } employee;